(1) Field of the Invention
The present invention relates to manufacturing of semiconductor devices in general, and in particular, to manufacturing of contact holes in semiconductor devices using a novel, single type, two-step Y-etching process.
(2) Description of the Related Art
Controlled manufacture of the shape and dimensions of holes through which connections are made between various components of integrated circuits in semiconductor substrates is very important, as is well known in the art. Holes are usually formed by etching through a dielectric layer that separates one or more layers of components of an integrated circuit. If the holes filled with metal connect conductive layers, they are referred to as via holes, and as contact holes if they connect the devices that are formed on the substrate.
A typical hole is shown in FIG. 1a. Here, hole (25), shown in phantom and in solid lines in FIG. 1b, is formed by etching dielectric layer (20), deposited on substrate (10) by well-known methods, through an opening (35) formed in photoresist layer (30). Photoresist layer (30) is later removed as shown in FIG. 1c. The shape of the hole entrance edge (23) in FIG. 1c is important because it determines how well the metal that is deposited later into the hole covers the edge of the entrance, usually known as step coverage (27). If step coverage (27) is poor, that is if metal (40) over the edge (23) is thin and variable as is usually the case with vertical holes as shown in FIG. 1c, then the metal may crack there causing reliability problems.
At the same time, the width of the contact area (50) of hole (25) over a device such as source or drain of a MOS structure shown in FIG. 1d is also important because, as is well known, the electrical contact resistance is determined by the size of the contact area. The larger the area, the smaller is the contact resistance. Hence, especially with today's ultra large scale integrated (ULSI) technology where the device sizes have been shrinking dramatically, the importance of the available area on a substrate has become even more critical. Shrinking in the lateral dimensions has also caused the aspect ratio (height over width) of the holes to increase, which in turn has made the forming, cleaning and filling of the holes that much more difficult. The method of forming holes disclosed in this invention addresses these problems.
Prior art also addresses some of these problems, but not in all aspects of the disclosure presented here. In addition to the structural characteristics, the nature of the process step and the number of process steps that are needed to form holes in a semiconductor substrate is important from the point of view of throughput and cost. Hsu in U.S. Pat. No. 5,552,343 teaches a method for forming tapered edges in order to improve step coverage over the edge of the hole. Sikora in U.S. Pat. No. 5,420,078 also teaches a method for varying the edge of a hole for the same reasons. However, both Hsu and Sikora use a wet etch and a dry etch which require two different process steps and two different chambers. Yamagata, et al. in U.S. Pat. No. 5,441,595 teaches still another method for forming tapered opening, but using a one-step dry etch. On the other hand, the dry etch used by Kim in U.S. Pat. No. 5,490,901 is of another type dry etch, but different from the methods of this invention. The method taught by this invention provides a combined tapered and straight contact or via hole formed by a single, two-step dry etch process thereby achieving good step coverage and maximum contact area when the hole is filled with metal.